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| r01ds0040ej0100 rev.1.00 page 1 of 58 feb 25, 2011 r8c/34k group renesas mcu datasheet 1.overview 1.1 features the r8c/34k group of single-chip mcus incorporates the r8c cpu core, employing sophisticated instructions for a high level of efficiency. with 1 mbyte of address sp ace, and it is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus are designed to maximize emi/ems performance. integration of many peripheral functions, including multifun ction timer and serial inte rface, reduces the number of system components. the r8c/34k group has data flash (1 kb 4 blocks ) with the background operation (bgo) function. 1.1.1 applications peripherals (usb applicable), audio components, camer as, televisions, household appliances, office equipment, communication devices, mobile devices, industrial equipment, and other applications. r01ds0040ej0100 rev.1.00 feb 25, 2011
r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 2 of 58 feb 25, 2011 1.1.2 specifications tables 1.1 and 1.2 outline the specifications for r8c/34k group. table 1.1 specifications for r8c/34k group (1) item function specification cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 1.8 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash refer to table 1.3 product list for r8c/34k group power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 (detection leve l of voltage detection 0 and voltage detection 1 selectable) i/o ports programmable i/o ports ? cmos i/o ports: 36, selectable pull-up resistor ? high current drive ports: 36 clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator pll frequency synthesizer ? oscillation stop detection: xin cl ock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (xin clock, pll frequency synthesizer, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode interrupts ? interrupt vectors: 69 ? external: 9 sources (int 5, key input 4) ? priority levels: 7 levels watchdog timer ? 14 bits 1 (with prescaler) ? reset start selectable ? low-speed on-chip oscillator for watchdog timer selectable dtc (data transfer controller) ? 1 channel ? activation sources: 30 ? transfer modes: 2 (no rmal mode, repeat mode) timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement m ode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot gene ration mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer rf 16 bits 1 input capture mode (input 1) output compare mode (output 4) serial interface uart0, uart1, uart3 clock synchronous serial i/o/uart 3 channel uart2 clock synchronous serial i/o, uart , multiprocessor communication function synchronous serial communication unit (ssu) 1 (shared with i 2 c bus) r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 3 of 58 feb 25, 2011 table 1.2 specifications for r8c/34k group (2) item function specification i 2 c bus 1 (shared with ssu) lin module hardware lin: 1 (timer ra, uart0) usb functions ? usb 2.0 specification compliant, full speed (12 mbps) supported ? usb device controller (udc), transceiver for usb2.0 are incorporated, and on-chip usb transceiver ? 5 pipes provided with individual fifo arbitrary ep numbers can be specified for pipe4 to 7 ? usb otg (on-the-go) operation is possible ? fifo size (total 448 bytes: dcp (ep0) = 64 bytes, pipe4 and pipe5 = 128 bytes (64-byte double buffer), pipe6 and pipe7 = 64 bytes ? supported transfer: dcp = control transfer in/out, pipe4 and pipe5 = bulk transfer in/out, pipe6 and pipe7 = interrupt transfer in/out ? when the host controller is selected automatic scheduling for sof and packet transmissions programmable intervals for interrupt transfers a/d converter 10-bit resolution 12 channels, includes sample and hold function, with sweep mode comparator b 2 circuits flash memory ? programming and eras ure voltage: vcc = 2.7 to 5.5 v ? programming and erasure endurance: 10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on -board flash rewrite function ? background operation (bgo) function (data flash) operating frequency/supply voltage f(xin) = 20 mhz (vcc = 2.7 to 5.5 v)(usb not used) f(xin) = 5 mhz (vcc = 1.8 to 5.5 v)(usb not used) current consumption typ. 7.0 ma (v cc = 5.0 v, f(xin) = 20 mhz) typ. 3.5 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 4.0 a (vcc = 3.0 v, wait mode) typ. 2.0 a (vcc = 3.0 v, stop mode) operating ambient temperature ? 20 to 85 c (n version) ? 40 to 85 c (d version) package 48-pin lqfp package code: plqp0048kb-a (previous code: 48p6q-a) r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 4 of 58 feb 25, 2011 1.2 product list table 1.3 lists product list for r8c/ 34k group. figure 1.1 shows a part number, memory size, and package of r8c/34k group. note: 1. the user rom is programmed before shipment. figure 1.1 part number, memory size, and package of r8c/34k group table 1.3 product list for r8c/34k group current of feb 2011 part no. rom capacity ram capacity package type remarks program rom data flash r5f21348knfp 64 kbytes 1 kbyte 4 8 kbytes plqp0048kb-a n version r5f2134cknfp 128kbytes 1 kbyte 4 10 kbytes plqp0048kb-a R5F21348KDFP 64 kbytes 1 kbyte 4 8 kbytes plqp0048kb-a d version r5f2134ckdfp 128kbytes 1 kbyte 4 10 kbytes plqp0048kb-a r5f21348knxxxfp 64 kbytes 1 kbyte 4 8 kbytes plqp0048kb-a n version factory programmin g product (1) r5f2134cknxxxfp 128kbytes 1 kbyte 4 10 kbytes plqp0048kb-a r5f21348kdxxxfp 64 kbytes 1 kbyte 4 8 kbytes plqp0048kb-a d version r5f2134ckdxxxfp 128kbytes 1 kbyte 4 10 kbytes plqp0048kb-a package type: fp: plqp0048kb-a rom number classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 8: 64 kb c: 128 kb r8c/34k group r8c/3x series memory type f: flash memory renesas mcu renesas semiconductor part no. r 5 f 21 34 8 k n xxx fp r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 5 of 58 feb 25, 2011 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram r8c cpu core memory rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator pll frequency synthesizer timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rf (16 bits 1) uart or clock synchronous serial i/o (8 bits 4) i 2 c bus or ssu (8 bits 1) peripheral functions watchdog timer (14 bits) comparator b voltage detection circuit dtc low-speed on-chip oscillator for watchdog timer 8 port p0 8 port p1 5 port p3 usb fifo (448 bytes) usb function (usb2.0 full speed) 4 port p6 2 port p7 4 port p8 port p4 5 notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. a/d converter (10 bits 12 channels) lin module r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 6 of 58 feb 25, 2011 1.4 pin assignment figure 1.3 shows pin assignment (top view). tables 1.4 and 1.5 outline the pin name information by pin number. figure 1.3 pin assignment (top view) 36 35 34 33 32 31 30 29 24 13 14 15 16 17 18 19 20 21 22 23 1 3 4 5 6 7 8 9 10 11 12 2 48 47 46 45 44 43 42 41 40 39 38 37 p0_7/an0(/trcioc) p0_6/an1(/trciod) p0_5/an2(/trciob) p0_4/an3(/trciob) p0_3/an4(/clk1/trciob) p0_2/an5(/rxd1/trcioa/trctrg) p0_1/an6(/txd1/trcioa/trctrg) p0_0/an7(/trcioa/trctrg) p8_3(/trfi/trfo10/rxd3) p8_2(/trfo02/txd3) p8_1(/trfo01/clk3) p8_0(/trfo00) 28 27 26 25 usb_drpd usb_dprpd usb_dpupe usb_vcc usb_dp usb_dm usb_vbus p7_6/usb_ovrcura p7_7/usb_vbusen p3_3/ivcmp3/scs(/cts2/rts2/trcclk) p3_4/ivref3/ssi(/trcioc) p3_5/scl/ssck(/trciod) p 1 _ 0 / a n 8 / k i 0 ( / t r c i o d ) p 1 _ 1 / a n 9 / k i 1 ( / t r c i o a / t r c t r g ) p 1 _ 2 / a n 1 0 / k l 2 ( / t r c i o b ) p 1 _ 3 / a n 1 1 / k l 3 / t r b o ( / t r c i o c ) p 1 _ 4 ( / t x d 0 / t r c c l k ) p 1 _ 5 ( / i n t 1 / r x d 0 / t r a i o ) p 1 _ 6 / i v r e f 1 ( / c l k 0 ) p 1 _ 7 / i v c m p 1 / i n t 1 ( / t r a i o ) p 4 _ 5 / a d t r g / i n t 0 ( / r x d 2 ) p 6 _ 5 / i n t 4 / u s b _ e x i c e n ( / c l k 2 / c l k 1 ) p 6 _ 6 / i n t 2 / u s b _ o v r c u r b ( / t x d 2 ) p 6 _ 7 / i n t 3 ( / u s b _ i d ( / t r c i o d ) r8c/34k group plqp0048kb-a (48p6q-a) (top view) p 6 _ 0 p 3 _ 0 ( / t r a o ) v r e f m o d e p 4 _ 3 p 4 _ 4 r e s e t p 4 _ 7 / x o u t v s s / a v s s p 4 _ 6 / x i n v c c / a v c c p 3 _ 7 / s d a / s s o / t r a o notes: 1. can be assigned to the pin in parentheses by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 7 of 58 feb 25, 2011 note: 1. can be assigned to the pin in parentheses by a program. table 1.4 pin name information by pin number (1) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus usb a/d converter, comparator b 1 p6_0 2 p3_0 (trao) 3 vref 4mode 5 p4_3 6 p4_4 7 reset 8 xout p4_7 9 vss/avss 10 xin p4_6 11 vcc/avcc 12 p3_7 trao sso sda 13 p3_5 (trciod) ssck scl 14 p3_4 (trcioc) ssi ivref3 15 p3_3 (trcclk) (cts2 /rts2 ) scs ivcmp3 16 p7_7 usb_vbusen 17 p7_6 usb_ovrcura 18 usb_vbus 19 usb_dm 20 usb_dp 21 usb_vcc 22 usb_dpupe 23 usb_dprpd 24 usb_drpd 25 p6_7 int3 (trciod) usb_id 26 p6_6 int2 (txd2) usb_ovrcurb 27 p6_5 int4 (clk2/clk1) usb_exicen 28 p4_5 int0 (rxd2) adtrg 29 p1_7 int1 (traio) ivcmp1 30 p1_6 (clk0) ivref1 31 p1_5 (int1 ) (traio) (rxd0) 32 p1_4 (trcclk) (txd0) 33 p1_3 ki 3 trbo (/trcioc) an11 34 p1_2 ki2 (trciob) an10 35 p1_1 ki1 (trcioa/ trctrg) an9 36 p1_0 ki0 (trciod) an8 37 p0_7 (trcioc) an0 38 p0_6 (trciod) an1 39 p0_5 (trciob) an2 40 p0_4 (trciob) an3 r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 8 of 58 feb 25, 2011 note: 1. can be assigned to the pin in parentheses by a program. table 1.5 pin name information by pin number (2) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus usb a/d converter, comparator b 41 p0_3 (trciob) (clk1) an4 42 p0_2 (trcioa/ trctrg) (rxd1) an5 43 p0_1 (trcioa/ trctrg) (txd1) an6 44 p0_0 (trcioa/ trctrg) an7 45 p8_3 (trfo10/ trfi) (rxd3) 46 p8_2 (trfo02) (txd3) 47 p8_1 (trfo01) (clk3) 48 p8_0 (trfo00) r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 9 of 58 feb 25, 2011 1.5 pin functions tables 1.6 and 1.7 list pin functions. i: input o: output i/o: input and output note: 1. refer to the oscillato r manufacturer for osc illation characteristics. table 1.6 pin functions (1) item pin name i/o type description power supply input vcc, vss ? apply 1.8 to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provided for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. (1) to use an external clock, input it to the xout pin and leave the xin pin open. xin clock output xout i/o int interrupt input int0 to int4 i int interrupt input pins. key input interrupt ki0 to ki3 i key input interrupt input pins. timer ra traio i/o timer ra i/o pin. trao o timer ra output pin. timer rb trbo o timer rb output pin. timer rc trcclk i external clock input pin. trctrg i external trigger input pin. trcioa, trciob, trcioc, trciod i/o timer rc i/o pins. timer rf trfi i timer rf input pins. trfo00, trfo10, trfo01, trfo02 o timer rf output pins. serial interface clk0, clk1, clk2, clk3 i/o transfer clock i/o pins. rxd0, rxd1, rxd2, rxd3 i serial data input pins. txd0, txd1, txd2, txd3 o serial data output pins. cts2 i transmission control input pin. rts2 o reception control output pin. ssu ssi i/o data i/o pin. scs i/o chip-select signal i/o pin. ssck i/o clock i/o pin. sso i/o data i/o pin. i 2 c bus scl i/o clock i/o pin. sda i/o data i/o pin. r8c/34k group 1. overview r01ds0040ej0100 rev.1.00 page 10 of 58 feb 25, 2011 i: input o: output i/o: input and output table 1.7 pin functions (2) item pin name i/o type description usb usb_dp/usb_dm i/o d+/d- i/o pins of the usb on-chip transceiver. connect these pins to the d+/d- pin of the usb bus. usb_vbus i usb cable connection monitor pin. connect this pin to vbus of the usb bus. whether vbus is connected or disconnected can be detected during operation as a function. usb_vbusen o vbus (5 v) supply enable signal for external power supply chip. usb_ovrcura/ usb_ovrcurb i external overcurrent detection signal should be connected to these pins. vbus comparator signals should be connected to these pins when the usb host power supply chip is connected. usb_dpupe o 1.5 k ? pull-up resistor control signal for usb d+ signal when operating as a function controller. usb_vcc i/o usb power supply pin. usb_dprpd/ usb_drpd o15 k ? pull-down resistor control signals for usb d+ and d- signals when operating as a host. usb_id i id input signal for microab or miniab connector should be connected when operating on otg. usb_exicen o low-power control signal for external power supply (otg) chip. connect this pin to the otg power supply ic to be connected externally. reference voltage input vref i reference voltage input pin to a/d converter. a/d converter an0 to an11 i analog input pins to a/d converter. adtrg i ad external trigger input pin. comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins. ivref1, ivref3 i comparator b reference voltage input pins. i/o port p0_0 to p0_7, p1_0 to p1_7, p3_0, p3_3 to p3_5, p3_7, p4_3 to p4_7, p6_0, p6_5 to p6_7, p7_6, p7_7, p8_0 to p8_3 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. r8c/34k group 2. central processing unit (cpu) r01ds0040ej0100 rev.1.00 page 11 of 58 feb 25, 2011 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1) r8c/34k group 2. central processing unit (cpu) r01ds0040ej0100 rev.1.00 page 12 of 58 feb 25, 2011 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, arithmetic, an d logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is analogous to a0. a1 can be combined w ith a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starti ng address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operati on results in an overflow; otherwise to 0. r8c/34k group 2. central processing unit (cpu) r01ds0040ej0100 rev.1.00 page 13 of 58 feb 25, 2011 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined. r8c/34k group 3. memory r01ds0040ej0100 rev.1.00 page 14 of 58 feb 25, 2011 3. memory 3.1 r8c/34k group figure 3.1 is a memory map of r8c/34k group. the r8 c/34k group has a 1-mbyte address space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower addresses, beginning with address 0ffffh. a 64-kbyte internal rom area is allocated addresses 04000h to 13fffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. the starting address of each interrupt routine is stored here. the internal rom (data flash) is al located addresses 03000h to 03fffh. the internal ram is allocated higher addresses, beginni ng with address 00400h. for example, a 8-kbyte internal ram area is allocated addresses 00400h to 023ffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfr s) are allocated addresses 00000h to 002ffh and 02c00h to 02fffh (the sfr areas for the dtc and other modules). peripheral function contro l registers are allocated here. all unallocated spaces within the sfrs are reserved and cannot be accessed by users. figure 3.1 memory map of r8c/34k group 0ffffh 0ffdch notes: 1. the data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kby te), and block d (1 kbyte). 2. the sfr areas for the dtc and other modules are allocated to addresses 02c0 0h to 02fffh. 3. the blank areas are reserved and cannot be accessed by users. internal ram size address 0xxxxh 8 kbytes 10 kbytes 023ffh 02bffh part number internal rom size address 0yyyyh r5f21348knfp, R5F21348KDFP r5f21348kn xxxfp, r5f 21348kdxxxfp 64 kbytes 128 kbytes 04000h 04000h address zzzzzh 13fffh 23fffh fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 02fffh 02c00h sfr (2) (refer to 4. special function registers (sfrs) ) zzzzzh 03fffh 03000h internal rom (data flash) (1) internal rom (program rom) undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor address break (reserved) reset r5f2134cknfp, r5f2134ckdfp r5f2134cknxxxfp, r5f213ckdxxxfp r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 15 of 58 feb 25, 2011 4. special function registers (sfrs) an sfr (special function regist er) is a control register for a peripheral function. tables 4.1 to 4.15 list the special function registers. table 4.16 lists the id code areas and option function select area. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. the cwr bit in the rstfr register is set to 0 after power-on and voltage monitor 0 reset. hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. the csproini bit in the ofs register is set to 0. 4. the lvdas bit in the ofs register is set to 1. 5. the lvdas bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 00101000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register mstcr 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source determination register rstfr 0xxxxxxxb (2) 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h 0011h 0012h 0013h 0014h 0015h high-speed on-chip oscillator control register 7 fra7 when shipping 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (3) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah high-speed on-chip oscillator control register 5 fra5 when shipping 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch 002dh 002eh 002fh high-speed on-chip oscillator control register 3 fra3 when shipping 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (4) 00100000b (5) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circuit control register vw0c 1100x010b (4) 1100x011b (5) 0039h voltage monitor 1 circuit control register vw1c 10001010b r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 16 of 58 feb 25, 2011 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h 0044h 0045h 0046h int4 interrupt control register int4ic xx00x000b 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h usb resume interrupt control register usbrsmic xxxxx000b 004ah 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register/iic bus interrupt control register (2) ssuic/iicic xxxxx000b 0050h timer rf compare 1 interrupt control register cmp1ic xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh timer rf interrupt control register trfic xxxxx000b 005ch timer rf compare 0 interrupt control register cmp0ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh uart2 bus collision detection interrupt control register u2bcnic xxxxx000b 005fh timer rf capture interrupt control register capic xxxxx000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh usb int interrupt control register usbintic xxxxx000b 006ch uart3 transmit interrupt control register s3ric xxxxx000b 006dh uart3 receive interrupt control register s3tic xxxxx000b 006eh 006fh 0070h 0071h 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 17 of 58 feb 25, 2011 table 4.3 sfr information (3) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0080h dtc activation control register dtctl 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dtc activation enable register 0 dtcen0 00h 0089h dtc activation enable register 1 dtcen1 00h 008ah dtc activation enable register 2 dtcen2 00h 008bh dtc activation enable register 3 dtcen3 00h 008ch 008dh dtc activation enable register 5 dtcen5 00h 008eh dtc activation enable register 6 dtcen6 00h 008fh 0090h timer rf register trf 00h 00h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah timer rf control register 0 trfcr0 00h 009bh timer rf control register 1 trfcr1 00h 009ch capture and compare 0 register trfm0 00h 00h 009dh 009eh compare 1 register trfm1 ffh ffh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh xxh 00a3h 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh xxh 00a7h 00a8h uart2 transmit/receive mode register u2mr 00h 00a9h uart2 bit rate register u2brg xxh 00aah uart2 transmit buffer register u2tb xxh xxh 00abh 00ach uart2 transmit/receive control register 0 u2c0 00001000b 00adh uart2 transmit/receive control register 1 u2c1 00000010b 00aeh uart2 receive buffer register u2rb xxh xxh 00afh 00b0h uart2 digital filter function select register urxdf 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh uart2 special mode register 5 u2smr5 00h 00bch 00bdh uart2 special mode register 3 u2smr3 000x0x0xb 00beh 00bfh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 18 of 58 feb 25, 2011 table 4.4 sfr information (4) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 00c0h a/d register 0 ad0 xxh 000000xxb 00c1h 00c2h a/d register 1 ad1 xxh 000000xxb 00c3h 00c4h a/d register 2 ad2 xxh 000000xxb 00c5h 00c6h a/d register 3 ad3 xxh 000000xxb 00c7h 00c8h a/d register 4 ad4 xxh 000000xxb 00c9h 00cah a/d register 5 ad5 xxh 000000xxb 00cbh 00cch a/d register 6 ad6 xxh 000000xxb 00cdh 00ceh a/d register 7 ad7 xxh 000000xxb 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 xxh 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech port p6 register p6 xxh 00edh port p7 register p7 xxh 00eeh port p6 direction register pd6 00h 00efh port p7 direction register pd7 00h 00f0h port p8 register p8 xxh 00f1h 00f2h port p8 direction register pd8 00h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 19 of 58 feb 25, 2011 table 4.5 sfr information (5) (1) note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h lin control register 2 lincr2 00h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011ah 011bh 011ch 011dh 011eh 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 00h 0127h 0128h timer rc general register a trcgra ffh ffh 0129h 012ah timer rc general register b trcgrb ffh ffh 012bh 012ch timer rc general register c trcgrc ffh ffh 012dh 012eh timer rc general register d trcgrd ffh ffh 012fh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 01111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 20 of 58 feb 25, 2011 table 4.6 sfr information (6) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h uart1 transmit/receive mode register u1mr 00h 0161h uart1 bit rate register u1brg xxh 0162h uart1 transmit buffer register u1tb xxh xxh 0163h 0164h uart1 transmit/receive control register 0 u1c0 00001000b 0165h uart1 transmit/receive control register 1 u1c1 00000010b 0166h uart1 receive buffer register u1rb xxh xxh 0167h 0168h uart3 transmit/receive mode register u3mr 00h 0169h uart3 bit rate register u3brg xxh 016ah uart3 transmit buffer register u3tb xxh xxh 016bh 016ch uart3 transmit/receive control register 0 u3c0 00001000b 016dh uart3 transmit/receive control register 1 u3c1 00000010b 016eh uart3 receive buffer register u3rb xxh xxh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 21 of 58 feb 25, 2011 table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 0180h timer ra pin select register trasr 00h 0181h timer rc pin select register trbrcsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h 0185h 0186h timer pin select register timsr 00h 0187h timer rf output control register trfout 00h 0188h uart0 pin select register u0sr 00h 0189h uart1 pin select register u1sr 00h 018ah uart2 pin select register 0 u2sr0 00h 018bh uart2 pin select register 1 u2sr1 00h 018ch ssu/iic pin select register ssuiicsr 00h 018dh 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h ss bit counter register ssbr 11111000b 0194h ss transmit data register l / iic bus transmit data register (2) sstdr / icdrt ffh 0195h ss transmit data register h (2) sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr / icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl / iccr2 01111101b 019ah ss mode register / iic bus mode register (2) ssmr / icmr 00010000b / 00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 019ch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 00h 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 22 of 58 feb 25, 2011 table 4.8 sfr information (8) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh xxh 0000xxxxb 01c1h 01c2h 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh xxh 0000xxxxb 01c5h 01c6h 01c7h address match interrupt enable register 1 aier1 00h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h pull-up control register 0 pur0 00h 01e1h pull-up control register 1 pur1 00h 01e2h pull-up control register 2 pur2 00h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h port p1 drive capacity control register p1drr 00h 01f1h 01f2h drive capacity control register 0 drr0 00h 01f3h drive capacity control register 1 drr1 00h 01f4h drive capacity control register 2 drr2 00h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h input threshold control register 2 vlt2 00h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh external input enable register 1 inten1 00h 01fch int input filter select register 0 intf 00h 01fdh int input filter select register 1 intf1 00h 01feh key input enable register 0 kien 00h 01ffh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 23 of 58 feb 25, 2011 table 4.9 sfr information (9) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2c00h dtc transfer vector area xxh 2c01h dtc transfer vector area xxh 2c02h dtc transfer vector area xxh 2c03h dtc transfer vector area xxh 2c04h dtc transfer vector area xxh 2c05h dtc transfer vector area xxh 2c06h dtc transfer vector area xxh 2c07h dtc transfer vector area xxh 2c08h dtc transfer vector area xxh 2c09h dtc transfer vector area xxh 2c0ah dtc transfer vector area xxh : dtc transfer vector area xxh : dtc transfer vector area xxh 2c3ah dtc transfer vector area xxh 2c3bh dtc transfer vector area xxh 2c3ch dtc transfer vector area xxh 2c3dh dtc transfer vector area xxh 2c3eh dtc transfer vector area xxh 2c3fh dtc transfer vector area xxh 2c40h dtc control data 0 dtcd0 xxh 2c41h xxh 2c42h xxh 2c43h xxh 2c44h xxh 2c45h xxh 2c46h xxh 2c47h xxh 2c48h dtc control data 1 dtcd1 xxh 2c49h xxh 2c4ah xxh 2c4bh xxh 2c4ch xxh 2c4dh xxh 2c4eh xxh 2c4fh xxh 2c50h dtc control data 2 dtcd2 xxh 2c51h xxh 2c52h xxh 2c53h xxh 2c54h xxh 2c55h xxh 2c56h xxh 2c57h xxh 2c58h dtc control data 3 dtcd3 xxh 2c59h xxh 2c5ah xxh 2c5bh xxh 2c5ch xxh 2c5dh xxh 2c5eh xxh 2c5fh xxh 2c60h dtc control data 4 dtcd4 xxh 2c61h xxh 2c62h xxh 2c63h xxh 2c64h xxh 2c65h xxh 2c66h xxh 2c67h xxh 2c68h dtc control data 5 dtcd5 xxh 2c69h xxh 2c6ah xxh 2c6bh xxh 2c6ch xxh 2c6dh xxh 2c6eh xxh 2c6fh xxh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 24 of 58 feb 25, 2011 table 4.10 sfr information (10) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2c70h dtc control data 6 dtcd6 xxh 2c71h xxh 2c72h xxh 2c73h xxh 2c74h xxh 2c75h xxh 2c76h xxh 2c77h xxh 2c78h dtc control data 7 dtcd7 xxh 2c79h xxh 2c7ah xxh 2c7bh xxh 2c7ch xxh 2c7dh xxh 2c7eh xxh 2c7fh xxh 2c80h dtc control data 8 dtcd8 xxh 2c81h xxh 2c82h xxh 2c83h xxh 2c84h xxh 2c85h xxh 2c86h xxh 2c87h xxh 2c88h dtc control data 9 dtcd9 xxh 2c89h xxh 2c8ah xxh 2c8bh xxh 2c8ch xxh 2c8dh xxh 2c8eh xxh 2c8fh xxh 2c90h dtc control data 10 dtcd10 xxh 2c91h xxh 2c92h xxh 2c93h xxh 2c94h xxh 2c95h xxh 2c96h xxh 2c97h xxh 2c98h dtc control data 11 dtcd11 xxh 2c99h xxh 2c9ah xxh 2c9bh xxh 2c9ch xxh 2c9dh xxh 2c9eh xxh 2c9fh xxh 2ca0h dtc control data 12 dtcd12 xxh 2ca1h xxh 2ca2h xxh 2ca3h xxh 2ca4h xxh 2ca5h xxh 2ca6h xxh 2ca7h xxh 2ca8h dtc control data 13 dtcd13 xxh 2ca9h xxh 2caah xxh 2cabh xxh 2cach xxh 2cadh xxh 2caeh xxh 2cafh xxh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 25 of 58 feb 25, 2011 table 4.11 sfr information (11) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2cb0h dtc control data 14 dtcd14 xxh 2cb1h xxh 2cb2h xxh 2cb3h xxh 2cb4h xxh 2cb5h xxh 2cb6h xxh 2cb7h xxh 2cb8h dtc control data 15 dtcd15 xxh 2cb9h xxh 2cbah xxh 2cbbh xxh 2cbch xxh 2cbdh xxh 2cbeh xxh 2cbfh xxh 2cc0h dtc control data 16 dtcd16 xxh 2cc1h xxh 2cc2h xxh 2cc3h xxh 2cc4h xxh 2cc5h xxh 2cc6h xxh 2cc7h xxh 2cc8h dtc control data 17 dtcd17 xxh 2cc9h xxh 2ccah xxh 2ccbh xxh 2ccch xxh 2ccdh xxh 2cceh xxh 2ccfh xxh 2cd0h dtc control data 18 dtcd18 xxh 2cd1h xxh 2cd2h xxh 2cd3h xxh 2cd4h xxh 2cd5h xxh 2cd6h xxh 2cd7h xxh 2cd8h dtc control data 19 dtcd19 xxh 2cd9h xxh 2cdah xxh 2cdbh xxh 2cdch xxh 2cddh xxh 2cdeh xxh 2cdfh xxh 2ce0h dtc control data 20 dtcd20 xxh 2ce1h xxh 2ce2h xxh 2ce3h xxh 2ce4h xxh 2ce5h xxh 2ce6h xxh 2ce7h xxh 2ce8h dtc control data 21 dtcd21 xxh 2ce9h xxh 2ceah xxh 2cebh xxh 2cech xxh 2cedh xxh 2ceeh xxh 2cefh xxh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 26 of 58 feb 25, 2011 table 4.12 sfr information (12) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2cf0h dtc control data 22 dtcd22 xxh 2cf1h xxh 2cf2h xxh 2cf3h xxh 2cf4h xxh 2cf5h xxh 2cf6h xxh 2cf7h xxh 2cf8h dtc control data 23 dtcd23 xxh 2cf9h xxh 2cfah xxh 2cfbh xxh 2cfch xxh 2cfdh xxh 2cfeh xxh 2cffh xxh 2d00h : 2dffh 2e00h system configuration control register syscfg 00h 00h 2e01h 2e02h 2e03h 2e04h system configuration status register 0 syssts0 00000x00b xx000000b 2e05h 2e06h 2e07h 2e08h device state control register 0 dvstctr0 00h 00h 2e09h 2e0ah 2e0bh 2e0ch 2e0dh 2e0eh 2e0fh 2e10h 2e11h 2e12h 2e13h 2e14h cfifo port register cfifo 00h 00h 2e15h 2e16h 2e17h 2e18h 2e19h 2e1ah 2e1bh 2e1ch 2e1dh 2e1eh 2e1fh 2e20h cfifo port select register cfifosel 00h 00h 2e21h 2e22h cfifo port control register cfifoctr 00h 00h 2e23h 2e24h 2e25h 2e26h 2e27h 2e28h 2e29h 2e2ah 2e2bh 2e2ch 2e2dh 2e2eh 2e2fh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 27 of 58 feb 25, 2011 table 4.13 sfr information (13) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2e30h interrupt enable register 0 intenb0 00h 00h 2e31h 2e32h interrupt enable register 1 intenb1 00h 00h 2e33h 2e34h 2e35h 2e36h brdy interrupt enable register brdyenb 00h 00h 2e37h 2e38h nrdy interrupt enable register nrdyenb 00h 00h 2e39h 2e3ah bemp interrupt enable register bempenb 00h 00h 2e3bh 2e3ch sof output configuration register sofcfg 00h 00h 2e3dh 2e3eh 2e3fh 2e40h interrupt status register 0 intsts0 x0000000b x0000000b 2e41h 2e42h interrupt status register 1 intsts1 00h 00h 2e43h 2e44h 2e45h 2e46h brdy interrupt status register brdysts 00h 00h 2e47h 2e48h nrdy interrupt status register nrdysts 00h 00h 2e49h 2e4ah bemp interrupt status register bempsts 00h 00h 2e4bh 2e4ch frame number register frmnum 00h 00h 2e4dh 2e4eh 2e4fh 2e50h usb address register usbaddr 00h 00h 2e51h 2e52h 2e53h 2e54h usb request type register usbreq 00h 00h 2e55h 2e56h usb request value register usbval 00h 00h 2e57h 2e58h usb request index register usbindx 00h 00h 2e59h 2e5ah usb request length register usbleng 00h 00h 2e5bh 2e5ch dcp configuration register dcpcfg 00h 00h 2e5dh 2e5eh dcp max packet size register dcpmaxp 00h 00h 2e5fh 2e60h dcp control register dcpctr 00h 00h 2e61h 2e62h 2e63h 2e64h pipe window select register pipesel 00h 00h 2e65h 2e66h 2e67h 2e68h pipe window configuration register pipecfg 00h 00h 2e69h 2e6ah 2e6bh 2e6ch pipe max packet size register pipemaxp 00h 00h 2e6dh 2e6eh pipe period control register pipeperi 00h 00h 2e6fh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 28 of 58 feb 25, 2011 table 4.14 sfr information (14) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2e70h 2e71h 2e72h 2e73h 2e74h 2e75h 2e76h pipe 4 control register pipe4ctr 00h 00h 2e77h 2e78h pipe 5 control register pipe5ctr 00h 00h 2e79h 2e7ah pipe 6 control register pipe6ctr 00h 00h 2e7bh 2e7ch pipe 7 control register pipe7ctr 00h 00h 2e7dh 2e7eh 2e7fh 2e80h : 2e8fh 2e90h 2e91h 2e92h 2e93h 2e94h 2e95h 2e96h 2e97h 2e98h 2e99h 2e9ah 2e9bh 2e9ch pipe 4 transaction counter enable register pipe4tre 00h 00h 2e9dh 2e9eh pipe 4 transaction counter register pipe4trn 00h 00h 2e9fh 2ea0h pipe 5 transaction counter enable register pipe5tre 00h 00h 2ea1h 2ea2h pipe 5 transaction counter register pipe5trn 00h 00h 2ea3h 2ea4h 2ea5h 2ea6h 2ea7h 2ea8h 2ea9h 2eaah 2eabh 2each 2eadh : 2ecfh 2ed0h device address 0 configuration register devadd0 00h 00h 2ed1h 2ed2h 2ed3h 2ed4h 2ed5h 2ed6h 2ed7h 2ed8h device address 4 configuration register devadd4 00h 00h 2ed9h 2edah device address 5 configuration register devadd5 00h 00h 2edbh 2edch 2eddh : 2effh r8c/34k group 4. special function registers (sfrs) r01ds0040ej0100 rev.1.00 page 29 of 58 feb 25, 2011 table 4.15 sfr information (15) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.16 id code areas and option function select area notes: 1. the option function select area is allocated in the flash memo ry, not in the sfrs. set appropria te values as rom data by a pr ogram. do not write additions to the option function select area. if the block including the option function select area is erased, th e option function select area is set to ffh. when blank products are shipped, the option function select area is set to ffh. it is set to the written value after written by the user. when factory-programming products are shipped, the value of the option function select area is the value programmed by the user . 2. the id code areas are allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not write additions to the id code areas. if the block includ ing the id code areas is erased, the id code areas are set to f fh. when blank products are shipped, the id code areas are set to ffh. they are set to the written value after written by the user. when factory-programming products are shipped, the value of the id code areas is the value programmed by the user. address register symbol after reset 2f00h usb module control register usbmc 00x10000b 2f01h pll control register 0 plc0 0010x000b 2f02h pll control register 1 plc1 00001100b 2f03h pll division control register pldiv 00001011b 2f04h 2f05h 2f06h 2f07h 2f08h 2f09h 2f0ah 2f0bh 2f0ch 2f0dh 2f0eh 2f0fh 2f10h usb pin select register 0 usbsr0 00h 2f11h usb pin select register 1 usbsr1 00h 2f12h uart3 pin select register u3sr 00h 2f13h 2f14h 2f15h 2f16h 2f17h 2f18h 2f19h 2f1ah 2f1bh 2f1ch 2f1dh 2f1eh 2f1fh : 2fffh address area name symbol after reset : ffdbh option function select register 2 ofs2 (note 1) : ffdfh id1 (note 2) : ffe3h id2 (note 2) : ffebh id3 (note 2) : ffefh id4 (note 2) : fff3h id5 (note 2) : fff7h id6 (note 2) : fffbh id7 (note 2) : ffffh option function select register ofs (note 1) r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 30 of 58 feb 25, 2011 5. electrical characteristics table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage ? 0.3 to v cc + 0.3 v v o output voltage ? 0.3 to v cc + 0.3 v p d power dissipation ? 40 c t opr 85 c500mw t opr operating ambient temperature ? 20 to 85 (n version)/ ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 31 of 58 feb 25, 2011 notes: 1. v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the average value of current measured during 100 ms. 3. foco40m can be used as the count s ource for timer rc in the range of v cc = 2.7 to 5.5 v. 4. connect v cc /av cc for the uv cc pin input. table 5.2 recommended operating conditions (1) symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage when usb function is used 3.0 5.0 5.5 v when usb function is not used 1.8 5.0 5.5 v uv cc usb supply voltage (when uvcc pin is input) when usb function is used v cc /av cc = 3.0 to 3.6 v ?v cc / av cc (4) ?v when usb function is not used v cc /av cc = 1.8 to 5.5 v ?v cc / av cc (4) ?v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage other than cmos input 0.8 v cc ?v cc v cmos input input level switching function (i/o port) input level selection: 0.35 v cc 4.0 v v cc 5.5 v 0.5 v cc ?v cc v 2.7 v v cc < 4.0 v 0.55 v cc ?v cc v 1.8 v v cc < 2.7 v 0.65 v cc ?v cc v input level selection: 0.5 v cc 4.0 v v cc 5.5 v 0.65 v cc ?v cc v 2.7 v v cc < 4.0 v 0.7 v cc ?v cc v 1.8 v v cc < 2.7 v 0.8 v cc ?v cc v input level selection: 0.7 v cc 4.0 v v cc 5.5 v 0.85 v cc ?v cc v 2.7 v v cc < 4.0 v 0.85 v cc ?v cc v 1.8 v v cc < 2.7 v 0.85 v cc ?v cc v external clock input (xout) 1.2 ? v cc v v il input ?l? voltage other than cmos input 0 ? 0.2 v cc v cmos input input level switching function (i/o port) input level selection: 0.35 v cc 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection: 0.5 v cc 4.0 v v cc 5.5 v 0 ? 0.4 v cc v 2.7 v v cc < 4.0 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection: 0.7 v cc 4.0 v v cc 5.5 v 0 ? 0.55 v cc v 2.7 v v cc < 4.0 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v external clock input (xout) 0 ? 0.4 v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? ? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? ? 80 ma i oh(peak) peak output ?h? current drive capacity low ? ? ? 10 ma drive capacity high ? ? ? 40 ma i oh(avg) average output ?h? current drive capacity low ? ? ? 5ma drive capacity high ? ? ? 20 ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ? ? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ??80ma i ol(peak) peak output ?l? current drive capacity low ? ? 10 ma drive capacity high ? ? 40 ma i ol(avg) average output ?l? current drive capacity low ? ? 5 ma drive capacity high ? ? 20 ma f (xin) xin clock input oscillation frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz foco40m when used as the count source for timer rc (3) 2.7 v v cc 5.5 v 32 ? 40 mhz foco-f foco-f frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz ? system clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz f (bclk) cpu clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 32 of 58 feb 25, 2011 figure 5.1 ports p0, p1, p3, p4, p6, p7 and p8 timing measurement circuit p0 p1 p3 p4 p6 p7 p8 30pf r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 33 of 58 feb 25, 2011 notes: 1. v cc /av cc = v ref = 2.2 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. the a/d conversion result will be undefined in wait mode, st op mode, when the flash memory stops, and in low-current- consumption mode. do not perform a/d conversion in these st ates or transition to these states during a/d conversion. 3. when the analog input voltage is over the reference voltage, th e a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. table 5.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ??10bit ? absolute accuracy 10-bit mode v ref = av cc = 5.0 v an0 to an7 input, an8 to an11 input ? ? 3 lsb v ref = av cc = 3.3 v an0 to an7 input, an8 to an11 input ? ? 5 lsb v ref = av cc = 3.0 v an0 to an7 input, an8 to an11 input ? ? 5 lsb v ref = av cc = 2.2 v an0 to an7 input, an8 to an11 input ? ? 5 lsb 8-bit mode v ref = av cc = 5.0 v an0 to an7 input, an8 to an11 input ? ? 2 lsb v ref = av cc = 3.3 v an0 to an7 input, an8 to an11 input ? ? 2 lsb v ref = av cc = 3.0 v an0 to an7 input, an8 to an11 input ? ? 2 lsb v ref = av cc = 2.2 v an0 to an7 input, an8 to an11 input ? ? 2 lsb ad a/d conversion clock 4.0 v v ref = av cc 5.5 v (2) 2?20mhz 3.2 v v ref = av cc 5.5 v (2) 2?16mhz 2.7 v v ref = av cc 5.5 v (2) 2?10mhz 2.2 v v ref = av cc 5.5 v (2) 2?5mhz ? tolerance level impedance ? 3 ? k ? t conv conversion time 10-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s 8-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s t samp sampling time ad = 20 mhz 0.8 ? ? s i vref v ref current v cc = 5.0 v, xin = f1 = ad = 20 mhz ? 45 ? a v ref reference voltage 2.2 ? av cc v via analog input voltage (3) 0? vref v ocvref on-chip reference voltage 2 mhz ad 4 mhz 1.19 1.34 1.49 v r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 34 of 58 feb 25, 2011 notes: 1. v cc = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. when the digital filter is disabled. table 5.4 comparator b electrical characteristics symbol parameter condition standard unit min. typ. max. v ref ivref1, ivref3 input reference voltage 0 ? v cc ? 1.4 v v i ivcmp1, ivcmp3 input voltage ? 0.3 ? v cc + 0.3 v ? offset ? 5 100 mv t d comparator output delay time (2) v i = v ref 100 mv ? 0.1 ? s i cmp comparator operating current v cc = 5.0 v ? 17.5 ? a r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 35 of 58 feb 25, 2011 note: 1. referenced to v cc = 3.0 to 5.5 v, uv cc = 3.0 v, at t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. figure 5.2 data signal timing diagram figure 5.3 load condition table 5.5 usb characteristics symbol parameter condition standard unit min. typ. max. v ih input characteristics input ?h? voltage figure 5.2 and 5.3 2.0 ? ? v v il input ?l? voltage ? ? 0.8 v v di differential input sensitivity 0.2 ? ? v v cm differential common mode range 0.8 ? 2.5 v v oh output characteristics output ?h? voltage figure 5.2 and 5.3 i ch = 200 a 2.8 ? ? v v ol output ?l? voltage figure 5.2 and 5.3 i cl = 2 ma ??0.3v v crs crossover voltage figure 5.2 and 5.3 1.3 ? 2.0 v t r rise time figure 5.2 and 5.3 4.0 ? 20.0 ns t f fall time figure 5.2 and 5.3 4.0 ? 20.0 ns t rfm rise time / fall time matching figure 5.2 and 5.3 (tr/tf) 90.0 ? 111.1 % z drv output resistance figure 5.2 and 5.3 includes r s = 27 ? 28 ? 44.0 ? uvcc uvcc output voltage v cc = 4.0 to 5.5v, pxxcon = vddusbe = 1 3.0 3.3 3.6 v pxxcon = 0 ? v cc ?v i susp consumption current of the internal power supply for usb v cc = 4.0 to 5.5 v uv cc - v ss 0.33 f v cc - v ss 0.1 f 50 a d+ d- v crs 90 % 90 % 10 % 10 % rising time falling time t r t f differential date lines d+ d- r s = 27 ?? test point test point r s = 27 ?? r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 36 of 58 feb 25, 2011 notes: 1. v cc = 2.7 to 5.5 v and t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 1,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after progr am and erase. (1 to min. value can be guaranteed.) 4. in a system that executes multiple programming operations, t he actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on t he erasure endurance of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.6 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 1,000 (3) ??times ? byte program time ? 80 500 s ? block erase time ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? s ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst -ready) time from when command is forcibly stopped until reading is enabled ?? 30 + cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ? ? year r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 37 of 58 feb 25, 2011 notes: 1. v cc = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each bl ock can be erased n times. fo r example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after progr am and erase. (1 to min. value can be guaranteed.) 4. in a system that executes multiple programming operations, t he actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, av eraging the erasure endurance between blocks a to d can further reduce the actual erasure endurance. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. ? 40 c for d version. 8. the data hold time includes time that the pow er supply is off or t he clock is not supplied. figure 5.4 time delay until suspend table 5.7 flash memory (data flash block a to block d) electric al characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ??times ? byte program time (program/erase endurance 1,000 times) ? 160 1500 s ? byte program time (program/erase endurance > 1,000 times) ? 300 1500 s ? block erase time (program/erase endurance 1,000 times) ?0.2 1 s ? block erase time (program/erase endurance > 1,000 times) ?0.3 1 s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? s ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst -ready) time from when command is forcibly stopped until reading is enabled ?? 30 + cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature ? 20 (7) ?85 c ? data hold time (8) ambient temperature = 55 c20 ? ? year fst6 bit suspend request (fmr21 bit) fixed time t d(sr-sus) clock-dependent time access restart fst6, fst7: bit in fst register fmr21: bit in fmr2 register fst7 bit r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 38 of 58 feb 25, 2011 notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version). 2. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. 4. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version). 2. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 3. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 4. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. table 5.8 voltage detection 0 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (2) 1.80 1.90 2.05 v voltage detection level vdet0_1 (2) 2.15 2.35 2.50 v voltage detection level vdet0_2 (2) 2.70 2.85 3.05 v voltage detection level vdet0_3 (2) 3.55 3.80 4.05 v ? voltage detection 0 circuit response time (4) at the falling of v cc from 5.0 v to (vdet0_0 ? 0.1) v ? 6 150 s ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 1.5 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.9 voltage detection 1 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_0 (2) at the falling of v cc 2.00 2.20 2.40 v voltage detection level vdet1_1 (2) at the falling of v cc 2.15 2.35 2.55 v voltage detection level vdet1_2 (2) at the falling of v cc 2.30 2.50 2.70 v voltage detection level vdet1_3 (2) at the falling of v cc 2.45 2.65 2.85 v voltage detection level vdet1_4 (2) at the falling of v cc 2.60 2.80 3.00 v voltage detection level vdet1_5 (2) at the falling of v cc 2.75 2.95 3.15 v voltage detection level vdet1_6 (2) at the falling of v cc 2.85 3.10 3.40 v voltage detection level vdet1_7 (2) at the falling of v cc 3.00 3.25 3.55 v voltage detection level vdet1_8 (2) at the falling of v cc 3.15 3.40 3.70 v voltage detection level vdet1_9 (2) at the falling of v cc 3.30 3.55 3.85 v voltage detection level vdet1_a (2) at the falling of v cc 3.45 3.70 4.00 v voltage detection level vdet1_b (2) at the falling of v cc 3.60 3.85 4.15 v voltage detection level vdet1_c (2) at the falling of v cc 3.75 4.00 4.30 v voltage detection level vdet1_d (2) at the falling of v cc 3.90 4.15 4.45 v voltage detection level vdet1_e (2) at the falling of v cc 4.05 4.30 4.60 v voltage detection level vdet1_f (2) at the falling of v cc 4.20 4.45 4.75 v ? hysteresis width at the rising of v cc in voltage detection 1 circuit vdet1_0 to vdet1_5 selected ?0.07? v vdet1_6 to vdet1_f selected ?0.10? v ? voltage detection 1 circuit response time (3) at the falling of v cc from 5.0 v to (vdet1_0 ? 0.1) v ? 60 150 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ? ? 100 s r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 39 of 58 feb 25, 2011 notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates a fter setting to 1 again after setting the vca27 bit in the vca2 register to 0. notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 5.5 power-on reset circuit electrical characteristics table 5.10 voltage detection 2 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 at the falling of v cc 3.70 4.00 4.30 v ? hysteresis width at the rising of v cc in voltage detection 2 circuit ?0.10? v ? voltage detection 2 circuit response time (2) at the falling of v cc from 5.0 v to (vdet2_0 ? 0.1) v ? 20 150 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.11 power-on reset circuit (2) symbol parameter condition standard unit min. typ. max. t rth external power v cc rise gradient (1) 0 ? 50,000 mv/msec notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 reset disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) external power v cc t rth t rth 1 f oco-s 32 1 f oco-s 32 r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 40 of 58 feb 25, 2011 notes: 1. v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. this enables the setting errors of bit rates such as 9600 bp s and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power supp ly generation circuit stab ilizes during power-on. table 5.12 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency after reset v cc = 1.8 v to 5.5 v ? 20 c topr 85 c 36.0 40 44.0 mhz v cc = 1.8 v to 5.5 v ? 40 c topr 85 c 36.0 40 44.0 high-speed on-chip oscillator frequency when the fra4 register correction value is written into the fra1 register and the fra5 register correction value into the fra3 register (2) v cc = 1.8 v to 5.5 v ? 20 c topr 85 c 33.178 36.864 40.550 mhz v cc = 1.8 v to 5.5 v ? 40 c topr 85 c 33.178 36.864 40.550 high-speed on-chip oscillator frequency when the fra6 register correction value is written into the fra1 register and the fra7 register correction value into the fra3 register v cc = 1.8 v to 5.5 v ? 20 c topr 85 c 28.8 32 35.2 mhz v cc = 1.8 v to 5.5 v ? 40 c topr 85 c 28.8 32 35.2 ? oscillation stability time v cc = 5.0 v, t opr = 25 c?0.53ms ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 5.13 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation stability time v cc = 5.0 v, t opr = 25 c ? 30 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a table 5.14 power supply circui t timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) ? ? 2,000 s r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 41 of 58 feb 25, 2011 notes: 1. v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.15 timing requirements of sync hronous serial communication unit (ssu) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ? ? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ? ? 1 t cyc (2) slave ? ? 1 s t fall ssck clock falling time master ? ? 1 t cyc (2) slave ? ? 1 s t su sso, ssi data input setup time 100 ? ? ns t h sso, ssi data input hold time 1 ? ? t cyc (2) t lead scs setup time slave 1t cyc + 50 ? ? ns t lag scs hold time slave 1t cyc + 50 ? ? ns t od sso, ssi data output delay time ? ? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 42 of 58 feb 25, 2011 figure 5.6 i/o timing of synchronous serial communication unit (ssu) (master) v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 43 of 58 feb 25, 2011 figure 5.7 i/o timing of synchronous seri al communication unit (ssu) (slave) v ih or v oh v il or v ol scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 44 of 58 feb 25, 2011 figure 5.8 i/o timing of synchronous serial communication unit (ssu) (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v il or v ol r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 45 of 58 feb 25, 2011 notes: 1. v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.9 i/o timing of i 2 c bus interface table 5.16 timing requirements of i 2 c bus interface symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ??ns t sclh scl input ?h? width 3t cyc + 300 (2) ??ns t scll scl input ?l? width 5t cyc + 500 (2) ??ns t sf scl, sda input fall time ? ? 300 ns t sp scl, sda input spike pulse rejection time ? ? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ??ns t stah start condition input hold time 3t cyc (2) ??ns t stas retransmit start condi tion input setup time 3t cyc (2) ??ns t stop stop condition input setup time 3t cyc (2) ??ns t sdas data input setup time 1t cyc + 40 (2) ??ns t sdah data input hold time 10 ? ? ns sda scl notes: 1. start condition 2. stop condition 3. retransmit start condition t buf v ih v il p (2) s (1) t stah t sclh t scll t sf t sr t scl t sdah sr (3) p (2) t sdas t stas t sp t stop r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 46 of 58 feb 25, 2011 note: 1. 4.2 v v cc 5.5 v, t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), and f(xin) = 20 mhz, unless otherwise specified. table 5.17 electrical characteristics (1) [4.2 v v cc 5.5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high v cc = 5 v i oh = ? 20 ma v cc ? 2.0 ? v cc v drive capacity low v cc = 5 v i oh = ? 5 ma v cc ? 2.0 ? v cc v xout v cc = 5 v i oh = ? 200 a1.0 ? v cc v v ol output ?l? voltage other than xout drive capacity high v cc = 5 v i ol = 20 ma ? ? 2.0 v drive capacity low v cc = 5 v i ol = 5 ma ? ? 2.0 v xout v cc = 5 v i ol = 200 a? ?0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio,trcioa, trciob, trcioc, trciod, trfi, usb_ovrcura, usb_vbus, usb_id, usb_ovrcurb, trctrg, trcclk, adtrg , rxd0, rxd1, rxd2, rxd3, clk0, clk1, clk2, clk3, cts2 , ssi, scl, sda, sso, ssck, scs 0.1 1.2 ? v reset 0.1 1.2 ? v i ih input ?h? current v i = 5 v, v cc = 5.0 v ? ? 5.0 a i il input ?l? current v i = 0 v, v cc = 5.0 v ? ? ? 5.0 a r pullup pull-up resistance v i = 0 v, v cc = 5.0 v 25 50 100 k ? r fxin feedback resistance xin ? 0.3 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 47 of 58 feb 25, 2011 table 5.18 electrical characteristics (2) [3.3 v v cc 5.5 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?6.515ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5.3 12.5 ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?3.6?ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?2.2?ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.5?ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz no division ?7.015ma xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16, mstiic = msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ?90400 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0, vca20 = 1 ?15100 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0, vca20 = 1 ?490 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0, vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.05.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?15? a r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 48 of 58 feb 25, 2011 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v, t opr = 25 c) figure 5.10 external clock input timing diagram when v cc = 5 v figure 5.11 traio input ti ming diagram when v cc = 5 v notes: 1. when using timer rf input capture mode, adjust the cycle time to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.12 trfi input timing diagram when v cc = 5 v table 5.19 external clock input (xout) symbol parameter standard unit min. max. t c(xout) xout input cycle time 50 ? ns t wh(xout) xout input ?h? width 24 ? ns t wl(xout) xout input ?l? width 24 ? ns table 5.20 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns table 5.21 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 400 (1) ?ns t wh(trfi) trfi input ?h? width 200 (2) ?ns t wl(trfi) trfi input ?l? width 200 (2) ?ns external clock input t wh(xout) t c(xout) t wl(xout) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio) t wh(trfi) t c(trfi) t wl(trfi) trfi input v cc = 5 v r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 49 of 58 feb 25, 2011 i = 0 to 3 figure 5.13 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.14 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 5 v table 5.22 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0?ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.23 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 250 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 250 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 to 3 v cc = 5 v inti input (i = 0 to 4) t w(inl) t w(inh) v cc = 5 v kii input (i = 0 to 3) r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 50 of 58 feb 25, 2011 note: 1. 2.7 v v cc < 4.2 v, t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), and f(xin) = 10 mhz, unless otherwise specified. 2. 3.0 v vcc < 3.6 v for the usb associated pins. table 5.24 electrical characteristics (3) [2.7 v v cc < 4.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high i oh = ? 5 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0 ? v cc v v ol output ?l? voltage other than xout drive capacity high i ol = 5 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v xout i ol = 200 a? ?0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trcioa, trciob, trcioc, trciod, trfi, usb_ovrcura, usb_vbus, usb_id, usb_ovrcurb, trctrg, trcclk, adtrg , rxd0, rxd1, rxd2, rxd3, clk0, clk1, clk2, clk3, cts2 , ssi, scl, sda, sso, ssck, scs v cc = 3.0 v 0.1 0.4 ? v reset v cc = 3.0 v 0.1 0.5 ? v i ih input ?h? current v i = 3 v, v cc = 3.0 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 3.0 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 3.0 v 42 84 168 k ? r fxin feedback resistance xin ? 0.3 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 51 of 58 feb 25, 2011 table 5.25 electrical characteristics (4) [2.7 v v cc < 3.3 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?3.510ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.57.5ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz no division ?7.015ma xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin clock off high-speed on-chip oscillator on foco-f = 10 mhz low-speed on-chip oscillator on = 125 khz no division ?4.0?ma xin clock off high-speed on-chip oscillator on foco-f = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.5?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16, mstiic = msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ?90390 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0, vca20 = 1 ?1590 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0, vca20 = 1 ?480 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0, vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.05.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?15? a r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 52 of 58 feb 25, 2011 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v, t opr = 25 c) figure 5.15 external clock input timing diagram when v cc = 3 v figure 5.16 traio input ti ming diagram when v cc = 3 v notes: 1. when using timer rf input capture mode, adjust the cycle time to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.17 trfi input timing diagram when v cc = 3 v table 5.26 external clock input (xout) symbol parameter standard unit min. max. t c(xout) xout input cycle time 50 ? ns t wh(xout) xout input ?h? width 24 ? ns t wl(xout) xout input ?l? width 24 ? ns table 5.27 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns table 5.28 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 1200 (1) ?ns t wh(trfi) trfi input ?h? width 600 (2) ?ns t wl(trfi) trfi input ?l? width 600 (2) ?ns external clock input t wh(xout) t c(xout) t wl(xout) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio) t wh(trfi) t c(trfi) t wl(trfi) trfi input v cc = 3 v r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 53 of 58 feb 25, 2011 i = 0 to 3 figure 5.18 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.19 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 3 v table 5.29 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0?ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.30 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 380 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 380 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 to 3 t w(inl) t w(inh) v cc = 3 v inti input (i = 0 to 4) kii input (i = 0 to 3) r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 54 of 58 feb 25, 2011 note: 1. 1.8 v v cc < 2.7 v, t opr = ? 20 to 85 c (n version)/-40 to 85 c (d version), and f(xin) = 5 mh z, unless otherwise specified. table 5.31 electrical characteristics (5) [1.8 v v cc < 2.7 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high i oh = ? 2 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0 ? v cc v v ol output ?l? voltage other than xout drive capacity high i ol = 2 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v xout i ol = 200 a? ?0.5v v t+- v t- hysteresis nt0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trcioa, trciob, trcioc, trciod, trfi, trctrg, trcclk, adtrg , rxd0, rxd1, rxd2, rxd3, clk0, clk1, clk2, clk3, cts2 , ssi, scl, sda, sso, ssck, scs 0.05 0.20 ? v reset 0.05 0.20 ? v i ih input ?h? current v i = 2.2 v, v cc = 2.2 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 2.2 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 2.2 v 70 140 300 k ? r fxin feedback resistance xin ? 0.3 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 55 of 58 feb 25, 2011 table 5.32 electrical characteristics (6) [1.8 v v cc < 2.7 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 1.8 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?2.2?ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?0.8?ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 5 mhz low-speed on-chip oscillator on = 125 khz no division ?2.510ma xin clock off high-speed on-chip oscillator on foco-f = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.7?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16, mstiic = msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ?90300 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0, vca20 = 1 ?1590 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0, vca20 = 1 ?480 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0, vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.0 5 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?15? a r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 56 of 58 feb 25, 2011 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v, t opr = 25 c) figure 5.20 external clock input timing diagram when v cc = 2.2 v figure 5.21 traio input ti ming diagram when v cc = 2.2 v notes: 1. when using timer rf input capture mode, adjust the cycle time to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.22 trfi input timing diagram when v cc = 2.2 v table 5.33 external clock input (xout) symbol parameter standard unit min. max. t c(xout) xout input cycle time 200 ? ns t wh(xout) xout input ?h? width 90 ? ns t wl(xout) xout input ?l? width 90 ? ns table 5.34 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns table 5.35 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 2000 (1) ?ns t wh(trfi) trfi input ?h? width 1000 (2) ?ns t wl(trfi) trfi input ?l? width 1000 (2) ?ns external clock input t wh(xout) t c(xout) t wl(xout) v cc = 2.2 v traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v t wh(trfi) t c(trfi) t wl(trfi) trfi input v cc = 2.2 v r8c/34k group 5. electrical characteristics r01ds0040ej0100 rev.1.00 page 57 of 58 feb 25, 2011 i = 0 to 3 figure 5.23 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.24 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 2.2 v table 5.36 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0?ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.37 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 1000 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 1000 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 to 3 t w(inl) t w(inh) v cc = 2.2 v inti input (i = 0 to 4) kii input (i = 0 to 3) r8c/34k group package dimensions r01ds0040ej0100 rev.1.00 page 58 of 58 feb 25, 2011 package dimensions diagrams showing the latest package dimensions and moun ting information are available in the ?p ackages? section of the renesas electronics website. terminal cross section b 1 c 1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. detail f l 1 c a l a 1 a 2 * 3 f 48 37 36 25 24 13 12 1 * 1 * 2 x index mark z e z d b p e h e h d d e previous code jeita package code renesas code plqp0048kb-a 48p6q-a mass[typ.] 0.2g p-lqfp48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s r8c/34k group datasheet c - 1 rev. date description page summary 0.01 nov 08, 2010 ? first edition issued 1.00 feb 25, 2011 all pages ?preliminary?, ?under development? deleted 3 table 1.2 revised 4 table 1.3, figure 1.1 revised 5 figure 1.2 revised 6 figure 1.3 revised 7 table 1.4 revised 9 table 1.6 revised 10 table 1.7 revised 14 3.1 revised, figure 3.1 ?part number? added 15 table 4.1 0026h revised 16 table 4.2 0050h, 005bh, 005ch and 005fh added 17 table 4.3 0090h and 00bbh revised 21 table 4.7 0181h revised 26 table 4.12 2e04h and 2e05h revised 27 table 4.13 2e3ch and 2e3dh added, 2e40h and 2e41h revised 28 table 4.14 2ed2h to 2ed7h deleted 29 table 4.15 2f04h and 2f13h deleted 30 to 57 5. electrical characteristics added all trademarks and registered tr ademarks are the property of their respective owners. revision history general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.0 |
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